Steep subthreshold swing or slope at cryogenic temperature is essential for n-FET and p-FET to reduce switching energy, power consumption and faster speed. Considering low subthreshold current low noise amplifier (LNA) being used for qubits fidelity detection and preservation in quantum computers, steep subthreshold slope that can be reduced as much as possible when the substrate temperature is close to 0 K or m K range is required for these LNA devices. But when measured in cryogenic conditions, almost all n-FET and p-FET structures fabricated in silicon show a positive subthreshold slope saturation which may be fluctuating but does not go to 0 as T is reduced hypothetically to 0 K. Some very good papers are available for authors [1-2] who focus on distortion of 3D continuous density of states (DOS) in n-FET and p-FET giving rise to band tails due to sparseness dopants and also severe incomplete ionization effects needing Fermi-Dirac integral based calculation for dopant ionization and channel carrier density under cryogenic temperature conditions. These papers also propose combination of thermionic emission, hopping and source to drain tunneling (SDT) as reasons behind subthreshold slope saturation. The authors in this paper show reasons behind why SDT approach is not viable when channel doping density is lower and drain voltage is also very low, an ideal condition for subthreshold slope’s experimental measurement and provide compelling reasons to consider for fluctuating subthreshold slope saturation value as summoned in the abstract.

Why SDT concept does not seem plausible and convincing?

First of all, for ultra-scaled n and p-FET fabricated in silicon, when the channel length is within 5 nm or less, at cryogenic temperature, gate to source barrier is naturally steep but due to lower channel doping needed for ballistic or semi-ballistic transport at cryogenic temperature, gate to drain potential drop profile is less steep also aided by lower drain potential within 100 mV. If the gate to drain potential profile is not also very steep but less steep according to the above explanation, direct tunneling width is enhanced so that SDT probability is lower and subthreshold slope saturation should not be dependent on this factor for consideration purpose.

Channel thickness variation that keeps residual carriers near the source to be removed from the source contact at a very low cryogenic temperature T.

Channel thickness variation at cryogenic temperature for n-FET and p-FET emanates from multiple sources. First of this is the random atomistic activated dopant distribution due to severe incomplete ionization at cryogenic temperature. This also causes sparseness in the channel carrier density as temperature is reduced close to 0 K. Additionally, density functional theory (DFT) based continuum theory for density of states (DOS) for conduction band and valence band fails and this single band minima or maxima generates tail bands close to conduction band in n-FET and valence band for p-FET.

High degree of interface traps can be generated in these tail bands as temperature is reduced to 0 K and as Fermi energy E_F moves up into the conduction band, these traps are occupied and can emit electrons into the source sided channel through hopping or trap assisted tunneling mechanism as gate voltage is lowered, reaching a steady state and contributor to excess carriers in the channel to be removed leading to subthreshold slope saturation When occupied by electrons, these interface traps screen the gate potential to penetrate into the depletion region and resist the depletion region to be wider as T is reduced so that C_D can be lowered. As C_D cannot be lowered at reduced T because of this effect, subthreshold slope cannot be lowered ( , Where the symbols have their usual meanings), additionally interface trap related capacitance as a function of surface band bending  where C_it (ψ_s) is interface trap related capacitance as these traps interact with channel carriers, gets added to the bracketed term). The worsening impact of cryogenic temperatures of introducing D_it (# number/cm²-eV) in the conduction band interfacial band tails of the order reaching 10¹²/cm²-eV, can result in  where the first q term is electronic charge in Coulomb and second q is normalized to unity eV , to 1.6 × 10^-7 F/cm² which is of the order of C_ox to a few 10^-7 F/cm² for generally 5-6 nm oxide thickness, so now  value is not a negligible fraction and can start additively to lift the SS value as T is lowered to a fluctuating saturation value.

The other cause of channel thickness variation and residual channel carriers at lower T as gate voltage is reduced, is the generation of electrons in the reverse biased depletion region underneath the channel for n-FET or holes for p-FET. Taking n-FET, these generated electrons as a result of high reverse field due to high surface band bending at cryogenic temperature, gets attracted by the gate positive charge and adds to the channel charge or carriers that are being removed as gate voltage is lowered at a lower T for SS evaluation. This is a plausible fact from observation, that due to severe incomplete ionization, N_A (ionized acceptors) for 10¹⁵/cm³ to 10¹⁶/cm³ at T = 300 K, can be around 10¹⁰/cm³ and if intrinsic carrier concentration decreases to 10⁶/cm³ around T = 4.2 K, minority carriers equivalent to ni²/N_A(ionized acceptors) can be 100/cm³ and considering the mean free path for momentum gain has been immensely prolonged at T = 4.2 K, these minority electrons will collide with high number of neutral dopant crystals in the depletion region and generate additional electrons and holes through impact ionization, where the holes are repelled by the positive gate potential and flow out through the substrate contact but electrons keep accumulating in the channel. Since, at steady states, these excess electrons will be always present in the channel, SS will keep on showing fluctuating characteristics as device temperature is lowered to cryogenic limit, i.e., 0 K.

Another cause for fluctuating subthreshold slope (swing) saturation value near 8 K or lower cryogenic temperature is due to quantum confinement of the thin silicon inversion layers for ultra scaled n-FET device. In this case the log (10) Ids-Vgs curve may show oscillations near 4.2 K due to subthreshold region mobility fluctuations caused by inter sub band scattering in the 2D quantum confinement direction of the n-FET device. Substrate biasing with small positive value, may shift the threshold voltage negatively and allow more charge injection from n+ source into channel and then occupying the lowest sub bands, inter sub band screening happens through this inversion charge and oscillations then can be very minute. Also, for thin silicon film, near intrinsic doping confirms full depletion of the device even at 8 K when incomplete ionization further reduces ionized dopant density and enhances depletion region width, then quantum confinement effect will be less severe.

We now analyze the effect of depletion region minority carriers such as electron in n-FET and hole in p-FET, getting attracted by the gate bias (positive for n-FET and negative for p-FET) towards the channel as the channel inversion carriers get removed by the source contact as temperature is reduced to cryogenic temperature. This will show through an approximate variation technique to deduction of a part of subthreshold slope or swing this factor can play a role.

First, in a one-sided reverse bias depletion region, the generation current is given by:

   (1)

Here, I_g generation current in a reverse biased depletion region taking n-FET case in A, q is electron charge, A is gate area ( taking 1micron channel length and 1 micron gate width, A = 10^-8 cm²), W_d is the depletion region width which gets widened in cryogenic temperature due to higher surface band bending at subthreshold due to severe incomplete ionization of substrate dopants and t_g is the minority carrier generation time, which is larger than 100 ms due to very reduced intrinsic carrier concentration n_i of silicon near T in the 10 K range.

The variational technique  can be applied to n_i variation from 10 K to 4.2 K. W_d variation from 10 K to 4.2 K and t_g variation from 10 K to 4.2 K. We assume in subthreshold region, gate voltage is reduced more to 0.1 V at 4.2 K from 0.15 V at 10 K. Hypothetically, n_i gets reduced from 6 ×  10² /cm³ to 10² /cm³. At 300 K, n_i is near 10¹⁰/cm³ and these reduction values are hypothetical depending on band gap increase and exponential reduction factor due to band gap of silicon as temperature is reduced. With this, we construct the variational equation:

 (2)

Here, t_g at 4.2 K is assumed 10^-4 s and from 10 K is variation in t_g is 2 % (Δt_g = 0.02 × 10^-4 s ) and W_d at 4. 2 K is 1.4 × 10^-4 cm and from T = 10 K, its variation is 2% (ΔW_d  = 0.02 × 1.4 × 10^-4 cm). Then substituting the terms, when from 10 K we reduce the current and gate voltage at 4. 2 K to compute:

 = -4.48 × 10^-26 + 4.48 × 10^-26 + 1.12 × 10^-23

Then, ΔI_d = 1.12 × 10^-23 × (0.1-0.15) = - 5.6 × 10^-25 A, which is right as the current in decreasing with a lowered current in 4.2 K.

In decade current normalization, this term is = 5.6 × 10^-25 A (absolute magnitude)/10^-10 A = 5.6 × 10^-15 per decade. Now taking base 10 logarithm of this term is log (5.6 × 10^-15) = -14.252

Finally, subthreshold swing SS = (0.1-0.15)/(-14.252) = 3.508 mV/decade

Ideally, near 10 K or above, the ΔI_d is higher than 4.2 K and hence logarithmic term is less negative and subthreshold swing S is increased and starts to create residual value that causes overall SS to deviate from linear reduction towards 0 value at T = 0 K which is predicted by Boltzmann thermionic emission based temperature reduction-subthreshold slope relationship.

Compelling additional device physics based insights bridge the gap between the articles referenced here where channel thickness variation near the source sided carrier removal, lifts the subthreshold slope (SS) or swing value to a positive number both for n-FET and p-FET (absolute positive number). The causes of this channel thickness variation are identified from additional well probed device physics based concepts. The analytical equations therefore have to take these additional insights into account for proper operation of cryogenic FETs and quantum computers we foresee in future.